1. Field
Exemplary embodiments of the present invention relate to an impedance control circuit.
2. Description of the Related Art
Diverse semiconductor devices formed of integrated circuit chips such as a Central Processing Unit (CPU), a memory, and a gate array are integrated with a variety of electrical devices such as a personal computer (PC), a server, and a workstation. Most semiconductor devices are equipped with a reception circuit for receiving diverse signals through an input pad and an output circuit for outputting internal signals through an output pad.
As the operation speeds of electrical devices become faster, the swing width of signals interfaced between semiconductor devices decrease gradually to minimize the delay time taken for signals to transfer. The narrower the swing width of a signal is, the more the signal is affected by external noise. Also, signal reflection originating from impedance mismatch at an interface node may affect the interfaced signal. The impedance mismatch is caused by external noise, variation of power source voltage, a change in operation temperature, a change in a fabrication process, and the like. Data may not be transferred at a fast rate due to the impedance mismatch. Also, the impedance mismatch may distort data outputted from a data output end of a semiconductor device. Therefore, setup/hold failure and input-voltage level indecision may be frequently caused when the semiconductor device receives a distorted output signal through the semiconductor device input.
Particularly, a semiconductor device featuring a fast operation speed adopts an impedance matching circuit, which is referred to as an on-die termination, around a pad in an integrated circuit chip to address some of the above described issues in signal transfer. According to a conventional on-die termination scheme, a source termination is performed in an output circuit of a transferring part, and a parallel termination is performed in a termination circuit that is coupled in parallel to the reception circuit coupled with the input pad.
ZQ calibration refers to a process for generating an impedance code that is used to maintain an impedance value at a target value although there is a change in the conditions of process, voltage and temperature (PVT). A termination impedance value is controlled based on the impedance code that is generated as a result of the ZQ calibration. Generally, a pad coupled with a reference resistor, which becomes a reference of a calibration operation, is referred to as a ZQ pad. The reference resistor is commonly called an external resistor because it is coupled outside of a chip.
Hereafter, an impedance control circuit for generating an impedance code is described. The impedance control circuit is also referred to as a calibration circuit.
FIG. 1 is a schematic view of a conventional impedance control circuit.
As shown in FIG. 1, the impedance control circuit includes a pull-up impedance unit 110, a dummy impedance unit 120, a pull-down impedance unit 130, comparators 102 and 103, and counters 104 and 105.
More specifically, the comparator 102 compares the voltage of a calibration node ZQ with a reference voltage VREF and generates an up signal UP or a down signal DN based on the comparison result. The voltage of the calibration node ZQ is generated from voltage distribution of the pull-up impedance unit 110 and the external resistor 101 coupled with a calibration pad. The reference voltage VREF is usually set to VDD/2. Here, the external resistor 101 is assumed to be of approximately 240Ω.
The counter 104 generates a pull-up impedance code PCODE<0:N> in response to the up/down signal UP/DN. The pull-up impedance code PCODE<0:N> adjusts the impedance value of the pull-up impedance unit 110 by turning on or off the parallel resistors inside of the pull-up impedance unit 110. Here, the parallel resistors are designed to have impedance values according to binary weight. The adjusted impedance value of the pull-up impedance unit 110 affects the voltage of the calibration node ZQ, and the above-described operation is repeated. The calibration operation repeats until the overall impedance value of the pull-up impedance unit 110 becomes the same as the impedance value of the external resistor 101. This is referred to as pull-up calibration.
The pull-up impedance code PCODE<0:N> is inputted to the dummy impedance unit 120 to decide the impedance value of the dummy impedance unit 120. From this point, a pull-down calibration operation begins. Just as the pull-up calibration operation, a calibration operation is performed using the comparator 103 and the counter 105 until the voltage of a node A becomes the same as the reference voltage VREF. This is referred to as pull-down calibration.
When the calibration operation is terminated, the pull-up impedance code PCODE<0:N>, which makes the external resistor 101 and the pull-up impedance unit 110 have the same impedance value, is generated, and a pull-down impedance code NCODE<0:N>, which makes the dummy impedance unit 120 and the pull-down impedance unit 130 have the same impedance value, is generated. The pull-up impedance code PCODE<0:N> and the pull-down impedance code NCODE<0:N> that are generated in the impedance control circuit are transferred to a termination circuit. The termination circuit terminates an interface code to adjust the impedance value of the termination circuit.
Referring to FIG. 1, the impedance value of the external resistor 101 is approximately 240Ω, and the target impedance values of the pull-up impedance unit 110 and the pull-down impedance unit 130 are approximately 240Ω too. In other words, the impedance value of the external resistor 101 and the target impedance values of the pull-up impedance unit 110 and the pull-down impedance unit 130 are the same.
However, there is a possibility that the calibration node ZQ may be coupled with an external resistor 101 having a different impedance value from the target impedance values of the pull-up impedance unit 110 and the pull-down impedance unit 130. For example, the target impedance values of the pull-up impedance unit 110 and the pull-down impedance unit 130 are approximately 240Ω, but the calibration node ZQ may be coupled with an external resistor 101 having a resistance of approximately 960Ω. Therefore, a method to generate accurate pull-up impedance code PCODE<0:N> and accurate pull-down impedance code NCODE<0:N> even though the external resistor 101 has a different impedance value from the target impedance values of the pull-up impedance unit 110 and the pull-down impedance unit 130 is desired.